Clock and Data Recovery (CDR) circuits form a part of Serializer-Deserializer (SerDes) receivers. Conventional CDR circuits can be designed to achieve bit-error-ratios (BER) on the order of 10−12 to 10−15 errors per bit. The CDR circuits use a sampling point that tracks the phase of a sampling clock based on some criterion, such as minimizing a Mean-Squared-Error (MSE). The optimal sampling point for CDR is the point at which a vertical eye opening is the largest. When the sampling phase is away from the optimal sampling point, the vertical eye margin is significantly reduced.
With enough jitter, a receiver can sample at a position where the vertical eye margin is not large enough to decode a bit correctly, causing bit errors. One conventional technique to avoid bit errors is to use a finite impulse response (FIR) filter on the transmitter side of a communication channel to reduce the pre-cursor inter-symbol interference (ISI). However, in optical communication modules, a FIR filter on the transmitter side is not possible. Consequently, in optical systems, pre-cursor ISI can only be cancelled at the receiver side of the communication channel.
The CDR circuits commonly used in receivers can be broadly classified into two categories, bang-bang CDR and baud-rate CDR. Each class has associated advantages and disadvantages. In a bang-bang, or Alexander type CDR circuit, a received signal is oversampled (i.e., sampled twice each symbol period). The symbol period is referred to as a Unit Interval (UI). Oversampling adds cost and complexity to the system. Oversampling requires a second clock having a 90 degrees phase difference from the data sampling clock and a separate capture latch to sample the received signal at crossings. The addition of the second clock and capture latch results in additional power and area for the receiver.
Ideally, one sample is obtained at a crossing boundary and another sample is obtained at a center of the slicer input eye. In a bang-bang CDR, the eye appears symmetric about the sampling point. The symmetric eye is desirable for good Sinusoidal Jitter Tolerance (SJT). SJT is the amplitude of sinusoidal jitter about the sampling point that can be tolerated without errors. However, better jitter tolerance comes at the cost of oversampling the signal. Two consecutive “center” data samples (i.e., d[k−1] and d[k]) and one crossing sample in-between (i.e., p[k]) are used to decide whether a current sampling phase is lagging or leading. The sampling phase is then corrected accordingly. Unlike baud-rate CDR, bang-bang CDR is not sensitive to pre-cursor ISI. However, making bang-bang CDR work with a Decision-Feedback Equalizer (DFE) based receiver is not trivial.
In a baud-rate CDR circuit, the received signal is sampled at the baud rate, or once every UI. Hence, oversampling does not occur in the baud-rate CDR circuit. The sampling phase can be chosen based on different criteria. For example, in an MMSE baud-rate CDR circuit, the sampling phase that yields a minimum MSE is chosen. In a Mueller-Muller baud-rate CDR circuit, the sampling phase is chosen such that a first pre-cursor of an equalized pulse and a first post-cursor of the equalized pulse are equal about the sampling point. The sampling point chosen can be at a point other than in the center of the equalized eye if the equalized pulse is not symmetrical in terms of first pre-cursor and first post-cursor.
Referring to FIG. 1, a diagram is shown illustrating a normalized graph of an unequalized channel impulse response 10 and an equalized channel impulse response 12. In a baud-rate CDR circuit where a convergence point (i.e., a settling point τ) relies on a first pre-cursor matching a first post-cursor (i.e., h(1)=h(−1), where h(1) is the first pre-cursor of the channel impulse response and h(−1) is the first post-cursor of the channel impulse response), a residual pre-cursor sample 14 (i.e., p−1(0)) can have a major impact on the settling point τ of a Mueller-Muller baud-rate CDR circuit. The residual pre-cursor sample 14 causes the Mueller-Muller baud-rate CDR circuit to shift the sampling phase to the left of the peak of the impulse response 10 (ideally the unequalized sample 16 at time=0) so that a first pre-cursor 18 (i.e., p−1(τ)), with respect to the sampling point τ, has an amplitude close to zero. Accordingly, the magnitude of a first post-cursor 20 (i.e., p1(0)) in the unequalized impulse response 10 increases from p1(0) to p1(τ) because of the shifting of the sampling phase to the left.
Referring to FIG. 2, an eye diagram is shown illustrating a conventional slicer input eye 30 of a Decision-Feedback Equalizer (DFE) receiver with un-cancelled pre-cursor inter-symbol interference (ISI). The DFE can cancel post-cursor ISI in the unequalized impulse response 10. Pre-cursor inter symbol interference (ISI) resulting from the communication channel can cause the baud-rate CDR circuit to settle to the left of the optimal sampling point of the received eye opening. The baud-rate CDR settles where h(1)=h(−1). With a decision feedback equalizer (DFE), h(1) is reduced to zero. However, in a conventional system h(−1) cannot be reduced to zero due to a lack of pre-cursor ISI cancellation. As a result, a phase of the baud-rate CDR moves left from the optimal sampling point on the impulse response until the point of h(1)=h(−1) is reached. When the sampling point moves left, h(1) slowly increases and h(−1) slowly decreases. The SJT (i.e., 2*HL) is reduced compared with the ideal sample point at time=0. Thus, in optical applications where a transmitter finite impulse response (TX-FIR) filter is not available, the Mueller-Muller baud-rate CDR suffers from poor SJT compared with the more costly and complex bang-bang CDR.
The resulting equalized impulse response 12 has the first pre-cursor sample 18 (i.e., pe−1(τ)=0) and a first equalized post-cursor sample 22 (i.e., pe+1(τ)=0). The superscript “e” is used herein to denote an equalized sample. The first pre-cursor sample 18 and the first equalized post-cursor sample 22 have magnitudes near zero. The conventional slicer input eye 30 is asymmetric about the sampling point τ. In particular, a left horizontal eye opening (i.e., HL) is smaller than a right horizontal eye opening (i.e., HR).
It would be desirable to have a baud-rate CDR receiver circuit that can provide pre-cursor ISI cancellation.